All posts by Gary Hillman

Owner and President of S-Cubed

Options in Lift-Off Processing

Lift off Processing considerations:

The lift off process provides a means of patterning metal by means of resist removal.  In the process a resist is deposited on the substrate surface, then lithographically patterned so that the non resist coated surfaces  which remain can then be filled with a seed layer, and followed by bulk material.

As the metal is not in intimate contact with the substrate surface where it has been deposited on the polymer/resist when the resist is dissolved away by a solvent such as Acetone or NMP, the metal on the polymer is “lifted off” leaving the patterned  material adhered to the substrate.   

One way to facilitate the “lifting-off”  is by using a LOR (lift-off resist) or an anti-reflective layer which acts as release layer. In these cases the develop process “undercuts” the resist so that the metal film is not continuous at the patterns edge.  The LOR material is soluble in NMP, and the process steps consist of hot soak and agitation of with NMP, followed by high pressure spray, and finally a IPA or IPA/water combination as the materials are miscible. It is important to note that the NMP must not be allowed to dry out between process steps.

Another methodology is using a single dyed resist layer, thereby allowing for an undercut of the side-wall on the resist profile. The resist is then simply removed by acetone or resist remover material, however mandates an anisotropic metal deposition, otherwise the solvent will not be able to ‘get’ at the resist. This process requires no more than high pressure solvent at room temperature (which can be recirculated), followed by fresh solvent to clean the wafer and replenish the solvent canister.

At S-Cubed we can configure our systems to run any combination of these processes. Removing the resist in an high pressure acetone/ resist remover bowl with recirculation, or by an NMP station, and IPA/aqueous station, or any combination of these modules for allowing for multiple lift-off processes. Or as discussed in our meeting, a simple Acetone soak and high pressure system.  The acetone release is simpler, and works well with compatible resists, whereas the NMP or DMSO type lift-off is more complicated, but is often preferred for fine geometries. 

Semiconductor Device Fabrication: Processes And Equipment

Fabrication processes are those steps required in the production of integrated circuits required for all the miraculous devices we use every day to communicate, to learn, to play and to work. They are a sequential set of tasks utilizing photolithographic and chemical processing techniques.

The circuits are created on wafers made from semiconductor materials most typically silicon. There are, however, other options available for certain specialized applications.

The process times are lengthy and the investment in both materials and machines is enormous, but the creation of value is far greater when the process is carried out with both accuracy and precision, on target and repeatable.

There are three principal things happening on the wafer that are:

  1. Adding material by depositing material
  2. Taking away material so as to leave behind the desired pattern of materials that create the circuit
  3. Modifying the character of the conductivity of the material

Some examples of the processes that add materials are:

  • Physical Vapor Deposition (evaporation or sputtering or the like)
  • Chemical Vapor Deposition (CVD)
  • Plasma enhanced CVD
  • Photoresist deposition
  • Polymer film deposition
  • Epitaxial depostion (meaning along the same axis so following the structure of the material, this is a special case of CVD)

Some examples of the processes that take away materials are:

  • Wet chemical etch
  • Wafer cleaning (this is to remove unwanted contaminants)
  • Dry etch typically using plasma technology
  • Photoresist develop (which itself is a sort of etch)
  • Chemical Mechanical Polishing

Some examples of the steps that modify the character of the conductivity of the material are:

Adding elements to the crystal structure of the material by:

  • Diffusion in a furnace
  • Injecting ions into the crystal structure by ion implantation, usually followed by an anneal step to “heal” the damage done by the implantation

Then there are the photolithographic steps and processes whose purpose it is to define where materials are and where they are not. It is this presence and absence that creates the pattern and therefore the function of the circuit.  These steps are called “Patterning”.


Includes processes that delineate, or otherwise alter the deposited and modified materials. Typically referred to as lithography, these processes often begin with wafer coating. Photoresists are used for this purpose.

Steppers focus, align and move the image of the mask or reticle. As a result, selected portions of wafer are exposed to the light. The exposed regions can then be washed away with a developer solution.

Following the etching and other sequential steps, photoresist is also removed from the wafer.

These processes may also be individually categorized as tuned for front-end-of-line (FEOL) processing and/or back-end-of-line (FEOL) processing steps.

S-Cubed’s semiconductor process equipment

At S-Cubed, you find an array of photolithography developers and photolithographic coaters, perfectly matching your high throughput requirements.

Scene 8 and Scene 12 photoresist processors support baking, coating and developing steps for up to 200mm and 300mm wafers, respectively.

You can opt for our combined wafer edge exposure and developing process automated module. It can be integrated with a coater and/or developer subsystem.

Our Versa Tool products can perform single wafer wet chemical cleans.

Our robotic tools help you achieve both inter-wafer and intra-wafer uniformity during both FEOL and BEOL wafer processing. Our experts are always available to answer your questions and help you find the right tools.  

Get in touch with us online or call at (973) 263-0640.

The Argument for New Vs Refurbished Used Photoresist Process Equipment

In an earlier BLOG we discussed “Lowering the Cost of Ownership (COO) of Spin Process Tools.” we did not discuss the fact that the customer does have an option to purchase a used, “used and refurbished” or “as is” version of a tool built at some point in the past as another means of lowering cost.

There are some obvious and immediate COO issues that come to mind when used equipment, sometimes more respectfully referred to as “legacy” equipment is purchased as opposed to new equipment. They include:

  • Very short warranty. Used or legacy equipment typically has a 30 to 90 day warranty, whereas today’s new equipment will often have a two-year warranty on components and one year on labor.
  • Availability of spares. Used equipment, some of which was built up to 30 years ago, is becoming more and more difficult to support as the electronic control means are often no longer in production. While this issue is mitigated when new controls are implemented on old platforms, however this adds to the overall cost.
  • Foot print issues. Equipment made before the advent of process stacking, typically done on the thermal modules, occupies more than twice the space as modern tools with Stacking. Used equipment that has stacking capability is often more expensive than new tools with stacking.
  • Installation Costs. Frequently it can cost as much to install a used tool as it cost to buy it. That is not the case with new equipment, where installation costs and facility costs are low.

In addition to the direct cost factors noted above, there are more subtle factors that come into play. Including:

  • Process support. New tools come with factory process support not typically available in used tools.
  • Software support. New tools can be “tweaked” to meet specific customer requirements, whereas used tools typically are not available with ANY software support or modification.
  • Capability to meet new process requirements that did not exist at the time of the design and manufacture of the used tool. Such factors as multiple movable dispenses, high reliability robots, hot plates designed to handle thicker photoresist films typically used in special purpose photolithography.
  • A great deal of the used “track” equipment was built before the advent of Semi Safety Standards and is difficult, if not impossible, to render safe.

The photoresist process equipment available today is low in cost and high in functionality and reliability. It can be tailored to the specific needs of the very specific customer who buys new and not used.

The Photolithography Process and Its Use In Wafer Level Chip Scale Packing (WLCSP)

The basic concept of Wafer Level Chip Scale Packaging (WLCSP) is to employ more or less the same techniques used in making a semiconductor device to create its packaged form. For convenience we will define the device manufacture as having been done in the Front End of the Line (FEOL) and the WLCSP packaging as being done in the Back End of the Line (BEOL). As in the manufacture of the device, the manufacture of the package is done en masse so that economy of scale minimizes cost and it is done in the same format namely on the wafer. There are however differences that arise that creates new needs in the photolithographic processing equipment that performs the Photolithography task. In this Blog we examine some of the most critical of those differences. We begin with the wafer itself.

The Wafer. The value of the wafer at this stage of the process is very high as it has been fully processed and the chips that make up the wafer are at their full value as functional devices. Also because all of the films needed to make a functional device up to that point have been applied the wafer is no longer a nearly perfectly flat object but is rather warped.

The character of the Photoresist to be applied. As the geometries to be created are rather large by comparison to those created in the FEOL the resist tends be far thicker and when bonding bumps are created the photoresist can be used to form a sort of mold into which the desired bump material is plated. In the BEOL resist thickness will typically be on the order of several microns up to 100 microns. The economics of packaging (BEOL) differ from those in the device (FEOL) manufacturing. Because geometries are generally larger lower cost resists can be used and often are. Photoresist processing equipment needs to accommodate these differences and must have a Low Cost of Ownership (Low COO) on a per wafer basis than FEOL tools.

Then the equipment should be able to handle warped wafers, with virtually NO wafer damage, it must be able to use thicker resists and perform the soft bake in an enclosure that does not need to be cleaned frequently if at all and it must be miserly in consumption of photoresist. The equipment itself should have high throughput, low footprint and low cost and material consumption.

Check out our other blogs discussing the BEOL from different points of view.

Lowering Cost of Ownership (COO) “Track” Tools in Back end of the Line (BEOL) Thick Resist Film processes

As it becomes apparent that the adoption of new process nodes has been significantly slowed down due to availability and cost of next generation FEOL lithography technologies, it becomes ever more important that the continuation of cost reductions and functionality improvements that have driven the growth of the Semiconductor industry over the last 40 years be sought elsewhere. Some of the investment heretofore focused on the FEOL “bleeding edge” technology should now be refocused more in BEOL Photo resist lithography for packing where the lower hanging fruit lies. This will require simplification of processes and reduction in material costs wherever possible while at the same time improving process control, yields and functionality and reducing photo resist processing tool costs.

One way to reduce costs is by substantially reducing waste in photolithographic processing technology. It has long been noted by just about anyone who performs spin processing on Photoresist Track equipment that there is an enormous amount of waste in the process as most of the Photoresist material consumed in the process is actually thrown off the wafer during the spin process and wasted. Textbooks in disusing the process point out the wastefulness of the process. The waste becomes especially meaningful in BEOL WLCSP, 2.5D and 3D processing where thicker resist films need to be cast. Multiple spins to achieve the film thickness required exacerbates the waste, while increasing Photoresist viscosity so that the thicker films can be cast adds substantially to equipment costs as the pumps required to pump the material can cost well into the 5 figures in US Dollars. Multiple spins also require more Photoresist track equipment for multiple trips through the equipment. The high viscosities also make elimination of bubbles a constant struggle further increasing costs. The film is formed during the spin process and then baked typically on a hot plate to remove additional solvent to render the film stable and photo definable. All of the foregoing tends to substantially increase photo resist processing costs in the Back End of the Line (BEOL) lithography for Wafer level Chip Scale Packaging (WLCSP). Another avenue is to use expensive chemically amplified resist (CAR) systems, which have the effect of improving CD control and aspect ratio’s in a single coat, however further increasing material cost substantially.

The engineers at S-Cubed™ have invented a new process…FastSpin™ that addresses all of these cost/complexity issues. In the new process (patents applied for) the film is not cast so much as wet formed by spinning the wafer under exquisite servo control for a very short time, subsequently processed to render the film stable and photo definable. The wet film is maintained in the wet state and is allowed to level, allowing for planar coatings over topography. The process not only substantially reduces photo resist consumption for both standard and CAR resists, it also substantially reduces the cost of the photo resist processing tools, Photo resist track, by reducing the number of spin processors required for a given spin processor tool throughput.

Please request further information regarding S-Cubed™ FastSpin™ click on the link:

Creating Value With “Track” Tools in Back end of the Line (BEOL)

The Semiconductor Industry has for years followed the path of “Moore’s” Law. Gordon Moore’s forecast that the industry would every 18 months double the number of transistors in a given area, thereby increasing value while reducing cost. His prediction has held true for about 20 years, and is now faltering. However the effect of his prediction can and will continue into the foreseeable future but rather than the aerial rule obtaining on silicon it will now move increasingly to the package. That trend is now beginning in earnest and the improvements in functionality and cost will occur more and more in the Back End of the Line (BEOL) /packaging of function. The driving economic factor is clearly the proliferation of mobile devices of all sorts.

While the technology of the photolithographic processing remains very similar there are important details that must be addressed if the tool sets of track and lithography are to be optimized for the new needs. BEOL processes involve different economic drivers, which must be accommodated by the Cost of Ownership (COO) models for BEOL tool sets versus Front End of Line (FEOL) tool sets. For more detail on the subject please see our BLOG entitled “Why Back End of Line (BEOL) Photoresist “Track” tool are and must be different from Front End of Line (FEOL) Photoresist processors.”

EUV Quo Vadis

“No tree grows to the sky”, my friend Karol Ubanek, the founder of Tencor, uttered these words of wisdom. They come to mind whenever I read an article or report on the subject of EUV. The amount of money and effort that are being poured into the development of the technology is nothing short of astonishing. One can only wonder what would happen if so much treasure was lavished not on the continuation of yesterday (smaller wavelengths equals smaller critical dimensions) but rather on totally tomorrow and different approaches to the problem of the continuation of the eternal “shrink” in semiconductor production. What if the answer wasn’t in the shrink but somewhere “outside the box”? TSV is such an attempt and so is 2.5 D packaging, occasionally referred to as 3.5D. . Maybe virtual wafers of epoxy rather than silicon eWLB style is the answer and then again maybe we are all trying to answer the wrong question. Is the question really to pack more devices into fewer square millimeters or is it really a better idea to “roll up the devices” as in a rolled up carpet, (there is a lot of visual information in a little bit of volume when the carpet is rolled up…just an example). It just seems to me if one half the money that is being spent on EUV was spent on seeking new questions and maybe getting new answers it could be more productive, after all… indeed, “no tree grows to the sky”.

Why Back End of Line (BEOL) Photoresist “Track” Tools are and must be Different from Front End of Line (FEOL) Photoresist Processors

In earlier writings we have discussed cost of ownership issues (COO) related to photoresist processing tools. In this entry, we will discuss the important functional differences between tools generally intended for the FEOL, and those more adaptable to the needs of BEOL wafer fabrication.

As the semiconductor industry has packed more and more functionality and speed into ever smaller chips (here one almost always must refer to Moore’s Law well know to those in the industry), the size and cost of the packaging of the chip has made necessary the creation of new types of wafer processing, which is needed to do wafer-level chip scale packaging. In this specific technology, photolithographic processing is used so chip outputs and inputs can be repositioned, so as to adapt to interconnect circuitry directly without the intervention of a typical pin out type package. In this case the chip is “rewired” and “bumped” so that it can be “flipped and bonded” directly to the chip interconnect circuitry. Such rewiring and wafer bumping is accomplished on the finished device wafer prior to singulation of the wafer into chips.

While the patterning concept is identical to that required to make the chip itself in practice, the geometries are far larger and the need for organic insulating film more prevalent than in the creation of the chip. This means that the spin cast films are much thicker and there is far more effluent of material leaving the wafer during the required “bakes” done in the thermal modules of the requisite tools. These thicker films require the following considerations in the design and implementation of the tool.

  • The cost of the process must be kept low, thus requiring tools with a low COO.
  • The spin cup must be designed to handle thicker films and capable of modulating spin exhaust conditions on a step-by-step basis throughout the process recipe.
  • The higher viscosity resists that are used to spin the thicker films means pumps must be geared to accomodate those viscosities.
  • The higher viscosity resist requires that the dispense height be preferably programmable rather than adjustable so that it can be varied during the dispense.
  • The much thicker films evolve far more solvent and other effluent requiring that the effluent be directed away from cold surfaces where it can condense and require frequent bake module cleaning, or create defective films owing to effluent reflux.

While FEOL tools may be utilized in BEOL, their high cost can be prohibitive, and their performance while tuned to the FEOL is not appropriate to the BEOL provider.

Lowering the Cost of Ownership (COO) of Spin Process Tools

In our last BLOG we discussed the need to lower the COO of the tools of production for those who are both designing and building their chips. The issue that we attempt to address here is how does one make that happen and at the same time improve functionality permitting the customer to do things that perhaps his competitor is not even aware of as a problem.

The aspects (solid dots below) and the responses (open dots below) to COO issues are:

  • The cost of the Bill of Materials (BOM) of the tool.
    • Employee identical hardware throughout the product line to improve economy of scale.
    • Minimize non-productive hardware, sensors and interconnect complexity.
    • Do not compromise on component quality, minimize the number of components.
  • Minimize Tool Footprint
    • Stack processes where it makes sense to do so
    • Integrate wafer handling and processes to eliminate wasted space
  • Maximize Reliability (note the very same responses to minimizing BOM costs improve reliability a clear Win-Win.
    • Employee identical hardware throughout the product line to improve economy of scale. (Enables testing and long term improvement)
    • Minimize non-productive hardware, sensors and interconnect complexity. (components that are not there cannot fail)
    • Do not compromise on component quality, minimize the number of components. (The highest quality components fail less frequently)
  • Minimize consumption of materials cost. (Things like photo resist, solvents, gases, etc.)
    • Improve tool functionality while lowering BOM cost
    • Creatively work with customers to take advantage of improved tool functionality.
    • Use software to improve functionality as well as hardware. Software has zero replication cost.
  • Increase Tool Throughput
    • Provide wafer handling capability at low cost that balances process times with minimum handling overhead time. Provide smart robotics capability.

Use “Small Grain” tools. By this we mean tools that can be provided in small increments of production while at the same time minimizing COO and Investment in absolute terms. All of the above items support this Aspect.

System Granularity and Management of Change and Growth

A very important aspect of cost of ownership (COO) of tools that include spin coaters and developers (often referred to a photoresist track tools) in the back end of line (BEOL), MEMS, and patterned sapphire substrate (PSS) processing-type processing lines is one that does not appear on the COO software packages. Often referred to as “opportunity cost,” it is specifically defined as “the difference in return between an investment one makes and another that one chose not to make.” A high degree of system “granularity” enables appropriate investment as customer needs evolve. Ultimately this can substantially reduce opportunity cost. Granularity specifically relates to tools sized to the capacity need, as well as properly balanced for output in order to minimize waste. Lets look at how that works, in the context of opportunity cost.

Since opportunity cost is always a comparison of the path chosen to the path that was not chosen, we will compare two hypothetical systems whose COO on a per wafer output basis is identical, but its granularity is different. Granularity will tend to go up in integer values. Let us suppose a system whose out put is equal to one unit of capacity, (i.e., 2000 wafers per month) and another whose out put is equal to two units of capacity (i.e., 4000 wafers per month). If the need is for one unit of capacity, then if the COO is the same and the more granular system is the clear choice. If it is two units of capacity then the choices are equal. However what happens when it is three units of capacity; then four; then five? Capacity needs often develop in incremental steps over the long term instead of in immediate doublings. The investment in the “granular approach” is obviously the more appropriate forward-thinking plan. As needs eventuate, so that capacity can be adjusted to market needs at the lowest possible cost in capital spread over time.