As the semiconductor industry continues on its inexorable path to classic transistor “shrink,” as predicted by Gordon Moore in his “Moore’s Law,” it has collided with the reality that while process shrinks are possible, they are no longer necessarily economical.
While circuit density might increase exponentially, so are the costs associated with such advances—all this in a time of growing need for legacy technology chips. Just possibly, this is the perfect time to get back to the “Blocking and Tackling” of high-volume manufacturing for chips in legacy markets. It might also be the time to explore how manufacturing costs can be minimized even further.
Semiconductor metrology for yield improvement
Let’s consider the following questions:
- To what extent can new semiconductor metrology and discovery technologies be applied at lower costs to reduce waste/improve yields? (Discovery technologies define problems, and the ONLY way to solve a problem is to define it.)
- Semiconductor integration solutions: To what extent can new semiconductor metrologies, discovery tools, and precision measurement of production/process parameters be integrated into process tools to render them intelligent producers at ever higher yields and predictability?
- How can we optimize process tool throughput and reliability while reducing tool cost, complexity, and footprint? To accomplish the former, one must ALSO do the latter.
First, we’ll explore questions 1 and 2, as they are clearly related.
Semiconductor yield enhancement solutions
When used in combination with data mining, collecting more robust data can provide a low-cost means by which yield-related learning can be achieved.
In order to discover yield and device performance relationships, what are some low/medium cost measurements that should be captured and analyzed?
- Semiconductor wafer processing solutions, e.g., temperature and humidity at the wafer ambient
- Flow rates and timing of all chemistries used in the process
- Process parameters, velocities, acceleration, physical position etc.
- Measurement and/or treatment of effluent volumes and characteristics as processes ensue
- Particle measurement equipment installed to track particulate and eliminate/minimize semiconductor contamination
As for question 3: How can we optimize semiconductor process tool throughput and reliability while reducing tool cost, complexity, and footprint?
Optimizing Process Tool Throughput While Reducing Cost, Complexity and Footprint
To achieve this, new thinking must be brought to bear. Tool architectures must go both up AND down. Tools today go up from a base line, but not down. Current semiconductor process robots are predominantly arranged horizontally, and then stacked one atop the other. The most expensive and least precise axis in any robotic handling system is Theta—the axis that sweeps through the most area. Theta moves take time.
Can and should Theta be eliminated? Where it makes sense to do so, why not? By thinking “outside the box” in these areas, we can substantially improve reliability while reducing cost and tool footprint. For more on this, see our other recent article on optimizing process robots—and contact us to learn more about our innovations in this space.
