Close this search box.

The Photolithography Process and Its Use In Wafer Level Chip Scale Packing (WLCSP)

The basic concept of Wafer Level Chip Scale Packaging (WLCSP) is to employ more or less the same techniques used in making a semiconductor device to create its packaged form. For convenience we will define the device manufacture as having been done in the Front End of the Line (FEOL) and the WLCSP packaging as being done in the Back End of the Line (BEOL). As in the manufacture of the device, the manufacture of the package is done en masse so that economy of scale minimizes cost and it is done in the same format namely on the wafer. There are however differences that arise that creates new needs in the photolithographic processing equipment that performs the Photolithography task. In this Blog we examine some of the most critical of those differences. We begin with the wafer itself.

The Wafer. The value of the wafer at this stage of the process is very high as it has been fully processed and the chips that make up the wafer are at their full value as functional devices. Also because all of the films needed to make a functional device up to that point have been applied the wafer is no longer a nearly perfectly flat object but is rather warped.

The character of the Photoresist to be applied. As the geometries to be created are rather large by comparison to those created in the FEOL the resist tends be far thicker and when bonding bumps are created the photoresist can be used to form a sort of mold into which the desired bump material is plated. In the BEOL resist thickness will typically be on the order of several microns up to 100 microns. The economics of packaging (BEOL) differ from those in the device (FEOL) manufacturing. Because geometries are generally larger lower cost resists can be used and often are. Photoresist processing equipment needs to accommodate these differences and must have a Low Cost of Ownership (Low COO) on a per wafer basis than FEOL tools.

Then the equipment should be able to handle warped wafers, with virtually NO wafer damage, it must be able to use thicker resists and perform the soft bake in an enclosure that does not need to be cleaned frequently if at all and it must be miserly in consumption of photoresist. The equipment itself should have high throughput, low footprint and low cost and material consumption.

Check out our other blogs discussing the BEOL from different points of view.

Ask Us a Questions?