Category Archives: Wafer Processing

The Photolithography Process and Its Use In Wafer Level Chip Scale Packing (WLCSP)

The basic concept of Wafer Level Chip Scale Packaging (WLCSP) is to employ more or less the same techniques used in making a semiconductor device to create its packaged form. For convenience we will define the device manufacture as having been done in the Front End of the Line (FEOL) and the WLCSP packaging as being done in the Back End of the Line (BEOL). As in the manufacture of the device, the manufacture of the package is done en masse so that economy of scale minimizes cost and it is done in the same format namely on the wafer. There are however differences that arise that creates new needs in the photolithographic processing equipment that performs the Photolithography task. In this Blog we examine some of the most critical of those differences. We begin with the wafer itself.

The Wafer. The value of the wafer at this stage of the process is very high as it has been fully processed and the chips that make up the wafer are at their full value as functional devices. Also because all of the films needed to make a functional device up to that point have been applied the wafer is no longer a nearly perfectly flat object but is rather warped.

The character of the Photoresist to be applied. As the geometries to be created are rather large by comparison to those created in the FEOL the resist tends be far thicker and when bonding bumps are created the photoresist can be used to form a sort of mold into which the desired bump material is plated. In the BEOL resist thickness will typically be on the order of several microns up to 100 microns. The economics of packaging (BEOL) differ from those in the device (FEOL) manufacturing. Because geometries are generally larger lower cost resists can be used and often are. Photoresist processing equipment needs to accommodate these differences and must have a Low Cost of Ownership (Low COO) on a per wafer basis than FEOL tools.

Then the equipment should be able to handle warped wafers, with virtually NO wafer damage, it must be able to use thicker resists and perform the soft bake in an enclosure that does not need to be cleaned frequently if at all and it must be miserly in consumption of photoresist. The equipment itself should have high throughput, low footprint and low cost and material consumption.

Check out our other blogs discussing the BEOL from different points of view.

Creating Value With “Track” Tools in Back end of the Line (BEOL)

The Semiconductor Industry has for years followed the path of “Moore’s” Law. Gordon Moore’s forecast that the industry would every 18 months double the number of transistors in a given area, thereby increasing value while reducing cost. His prediction has held true for about 20 years, and is now faltering. However the effect of his prediction can and will continue into the foreseeable future but rather than the aerial rule obtaining on silicon it will now move increasingly to the package. That trend is now beginning in earnest and the improvements in functionality and cost will occur more and more in the Back End of the Line (BEOL) /packaging of function. The driving economic factor is clearly the proliferation of mobile devices of all sorts.

While the technology of the photolithographic processing remains very similar there are important details that must be addressed if the tool sets of track and lithography are to be optimized for the new needs. BEOL processes involve different economic drivers, which must be accommodated by the Cost of Ownership (COO) models for BEOL tool sets versus Front End of Line (FEOL) tool sets. For more detail on the subject please see our BLOG entitled “Why Back End of Line (BEOL) Photoresist “Track” tool are and must be different from Front End of Line (FEOL) Photoresist processors.”

Lowering the Cost of Ownership (COO) of Spin Process Tools

In our last BLOG we discussed the need to lower the COO of the tools of production for those who are both designing and building their chips. The issue that we attempt to address here is how does one make that happen and at the same time improve functionality permitting the customer to do things that perhaps his competitor is not even aware of as a problem.

The aspects (solid dots below) and the responses (open dots below) to COO issues are:

  • The cost of the Bill of Materials (BOM) of the tool.
    • Employee identical hardware throughout the product line to improve economy of scale.
    • Minimize non-productive hardware, sensors and interconnect complexity.
    • Do not compromise on component quality, minimize the number of components.
  • Minimize Tool Footprint
    • Stack processes where it makes sense to do so
    • Integrate wafer handling and processes to eliminate wasted space
  • Maximize Reliability (note the very same responses to minimizing BOM costs improve reliability a clear Win-Win.
    • Employee identical hardware throughout the product line to improve economy of scale. (Enables testing and long term improvement)
    • Minimize non-productive hardware, sensors and interconnect complexity. (components that are not there cannot fail)
    • Do not compromise on component quality, minimize the number of components. (The highest quality components fail less frequently)
  • Minimize consumption of materials cost. (Things like photo resist, solvents, gases, etc.)
    • Improve tool functionality while lowering BOM cost
    • Creatively work with customers to take advantage of improved tool functionality.
    • Use software to improve functionality as well as hardware. Software has zero replication cost.
  • Increase Tool Throughput
    • Provide wafer handling capability at low cost that balances process times with minimum handling overhead time. Provide smart robotics capability.

Use “Small Grain” tools. By this we mean tools that can be provided in small increments of production while at the same time minimizing COO and Investment in absolute terms. All of the above items support this Aspect.