The Semiconductor Industry has for years followed the path of “Moore’s” Law. Gordon Moore’s forecast that the industry would every 18 months double the number of transistors in a given area, thereby increasing value while reducing cost. His prediction has held true for about 20 years, and is now faltering. However the effect of his prediction can and will continue into the foreseeable future but rather than the aerial rule obtaining on silicon it will now move increasingly to the package. That trend is now beginning in earnest and the improvements in functionality and cost will occur more and more in the Back End of the Line (BEOL) /packaging of function. The driving economic factor is clearly the proliferation of mobile devices of all sorts.
While the technology of the photolithographic processing remains very similar there are important details that must be addressed if the tool sets of track and lithography are to be optimized for the new needs. BEOL processes involve different economic drivers, which must be accommodated by the Cost of Ownership (COO) models for BEOL tool sets versus Front End of Line (FEOL) tool sets. For more detail on the subject please see our BLOG entitled “Why Back End of Line (BEOL) Photoresist “Track” tool are and must be different from Front End of Line (FEOL) Photoresist processors.”
In earlier writings we have discussed cost of ownership issues (COO) related to photoresist processing tools. In this entry, we will discuss the important functional differences between tools generally intended for the FEOL, and those more adaptable to the needs of BEOL wafer fabrication.
As the semiconductor industry has packed more and more functionality and speed into ever smaller chips (here one almost always must refer to Moore’s Law well know to those in the industry), the size and cost of the packaging of the chip has made necessary the creation of new types of wafer processing, which is needed to do wafer-level chip scale packaging. In this specific technology, photolithographic processing is used so chip outputs and inputs can be repositioned, so as to adapt to interconnect circuitry directly without the intervention of a typical pin out type package. In this case the chip is “rewired” and “bumped” so that it can be “flipped and bonded” directly to the chip interconnect circuitry. Such rewiring and wafer bumping is accomplished on the finished device wafer prior to singulation of the wafer into chips.
While the patterning concept is identical to that required to make the chip itself in practice, the geometries are far larger and the need for organic insulating film more prevalent than in the creation of the chip. This means that the spin cast films are much thicker and there is far more effluent of material leaving the wafer during the required “bakes” done in the thermal modules of the requisite tools. These thicker films require the following considerations in the design and implementation of the tool.
- The cost of the process must be kept low, thus requiring tools with a low COO.
- The spin cup must be designed to handle thicker films and capable of modulating spin exhaust conditions on a step-by-step basis throughout the process recipe.
- The higher viscosity resists that are used to spin the thicker films means pumps must be geared to accomodate those viscosities.
- The higher viscosity resist requires that the dispense height be preferably programmable rather than adjustable so that it can be varied during the dispense.
- The much thicker films evolve far more solvent and other effluent requiring that the effluent be directed away from cold surfaces where it can condense and require frequent bake module cleaning, or create defective films owing to effluent reflux.
While FEOL tools may be utilized in BEOL, their high cost can be prohibitive, and their performance while tuned to the FEOL is not appropriate to the BEOL provider.
In our last BLOG we discussed the need to lower the COO of the tools of production for those who are both designing and building their chips. The issue that we attempt to address here is how does one make that happen and at the same time improve functionality permitting the customer to do things that perhaps his competitor is not even aware of as a problem.
The aspects (solid dots below) and the responses (open dots below) to COO issues are:
- The cost of the Bill of Materials (BOM) of the tool.
- Employee identical hardware throughout the product line to improve economy of scale.
- Minimize non-productive hardware, sensors and interconnect complexity.
- Do not compromise on component quality, minimize the number of components.
- Minimize Tool Footprint
- Stack processes where it makes sense to do so
- Integrate wafer handling and processes to eliminate wasted space
- Maximize Reliability (note the very same responses to minimizing BOM costs improve reliability a clear Win-Win.
- Employee identical hardware throughout the product line to improve economy of scale. (Enables testing and long term improvement)
- Minimize non-productive hardware, sensors and interconnect complexity. (components that are not there cannot fail)
- Do not compromise on component quality, minimize the number of components. (The highest quality components fail less frequently)
- Minimize consumption of materials cost. (Things like photo resist, solvents, gases, etc.)
- Improve tool functionality while lowering BOM cost
- Creatively work with customers to take advantage of improved tool functionality.
- Use software to improve functionality as well as hardware. Software has zero replication cost.
- Increase Tool Throughput
- Provide wafer handling capability at low cost that balances process times with minimum handling overhead time. Provide smart robotics capability.
Use “Small Grain” tools. By this we mean tools that can be provided in small increments of production while at the same time minimizing COO and Investment in absolute terms. All of the above items support this Aspect.
In our first post, we made the following point about companies that are not the huge Foundries; “such companies will use their own creativity and drive to gain a market advantage owing to their expertise in both designing and building their chips. Such companies will need to find ways to lower their manufacturing costs by effectively lowering the cost of ownership of the tools of production.” Another way to make this argument is that those companies must innovate.
But wait. Everyone knows that we all need to be data driven. We need to have the data that successfully makes the argument that the innovation is working successfully. It is sort of a “chicken and egg” dilemma. If we had the data, then it’s been done and if we don’t have the data we can’t proceed. Ultimately, we have to start someplace. The question is always “where?”
First, we need to start with a better understanding of nature. When all else fails, we as professionals should be thinking through what nature wants to happen. The study of chemistry and the laws of thermodynamics in the discipline of physical chemistry can, and should, instruct us and provide the bridge that we build to cross from no data to innovation; and from innovation, to new data that can provide that lower cost of ownership so vital to the companies that must be creative. Ultimately, it is that creativity that helps to foster success.
Does the word “commodity” come to mind; how about the word “innovation?” OK, now try “risk.” The question of the outlook for semiconductor production worldwide is a mixture of the feelings and fears, thoughts and challenges associated with the relationship between those three words, Commodity, Innovation and Risk…
Now look at the Global Semiconductor Industry and the rise and subsequent consolidation of the Foundries that now dominate the latest mass production semiconductor technologies. There are three possibly four left standing, TSMC, Global Foundries, Samsung and perhaps Intel will enter the battle. The risks of technological advance in the manufacture, as opposed to design, of semiconductors are being born by the foundries. Their hard earned and costly manufacturing skills will be generally available to all who pay the price and have the manufacturing volumes that justify the costly tooling and sustaining engineering.
What of those, who for good reasons of their own, will not or cannot utilize the giant foundries. Such companies will use their own creativity and drive to gain a market advantage owing to their expertise in both designing and building their chips. Such companies will need to find ways to lower their manufacturing costs by effectively lowering the cost of ownership of the tools of production.