As it becomes apparent that the adoption of new process nodes has been significantly slowed down due to availability and cost of next generation FEOL lithography technologies, it becomes ever more important that the continuation of cost reductions and functionality improvements that have driven the growth of the Semiconductor industry over the last 40 years be sought elsewhere. Some of the investment heretofore focused on the FEOL “bleeding edge” technology should now be refocused more in BEOL Photo resist lithography for packing where the lower hanging fruit lies. This will require simplification of processes and reduction in material costs wherever possible while at the same time improving process control, yields and functionality and reducing photo resist processing tool costs.
One way to reduce costs is by substantially reducing waste in photolithographic processing technology. It has long been noted by just about anyone who performs spin processing on Photoresist Track equipment that there is an enormous amount of waste in the process as most of the Photoresist material consumed in the process is actually thrown off the wafer during the spin process and wasted. Textbooks in disusing the process point out the wastefulness of the process. The waste becomes especially meaningful in BEOL WLCSP, 2.5D and 3D processing where thicker resist films need to be cast. Multiple spins to achieve the film thickness required exacerbates the waste, while increasing Photoresist viscosity so that the thicker films can be cast adds substantially to equipment costs as the pumps required to pump the material can cost well into the 5 figures in US Dollars. Multiple spins also require more Photoresist track equipment for multiple trips through the equipment. The high viscosities also make elimination of bubbles a constant struggle further increasing costs. The film is formed during the spin process and then baked typically on a hot plate to remove additional solvent to render the film stable and photo definable. All of the foregoing tends to substantially increase photo resist processing costs in the Back End of the Line (BEOL) lithography for Wafer level Chip Scale Packaging (WLCSP). Another avenue is to use expensive chemically amplified resist (CAR) systems, which have the effect of improving CD control and aspect ratio’s in a single coat, however further increasing material cost substantially.
The engineers at S-Cubed™ have invented a new process…FastSpin™ that addresses all of these cost/complexity issues. In the new process (patents applied for) the film is not cast so much as wet formed by spinning the wafer under exquisite servo control for a very short time, subsequently processed to render the film stable and photo definable. The wet film is maintained in the wet state and is allowed to level, allowing for planar coatings over topography. The process not only substantially reduces photo resist consumption for both standard and CAR resists, it also substantially reduces the cost of the photo resist processing tools, Photo resist track, by reducing the number of spin processors required for a given spin processor tool throughput.
Please request further information regarding S-Cubed™ FastSpin™ click on the link:
The Semiconductor Industry has for years followed the path of “Moore’s” Law. Gordon Moore’s forecast that the industry would every 18 months double the number of transistors in a given area, thereby increasing value while reducing cost. His prediction has held true for about 20 years, and is now faltering. However the effect of his prediction can and will continue into the foreseeable future but rather than the aerial rule obtaining on silicon it will now move increasingly to the package. That trend is now beginning in earnest and the improvements in functionality and cost will occur more and more in the Back End of the Line (BEOL) /packaging of function. The driving economic factor is clearly the proliferation of mobile devices of all sorts.
While the technology of the photolithographic processing remains very similar there are important details that must be addressed if the tool sets of track and lithography are to be optimized for the new needs. BEOL processes involve different economic drivers, which must be accommodated by the Cost of Ownership (COO) models for BEOL tool sets versus Front End of Line (FEOL) tool sets. For more detail on the subject please see our BLOG entitled “Why Back End of Line (BEOL) Photoresist “Track” tool are and must be different from Front End of Line (FEOL) Photoresist processors.”
In our last BLOG we discussed the need to lower the COO of the tools of production for those who are both designing and building their chips. The issue that we attempt to address here is how does one make that happen and at the same time improve functionality permitting the customer to do things that perhaps his competitor is not even aware of as a problem.
The aspects (solid dots below) and the responses (open dots below) to COO issues are:
- The cost of the Bill of Materials (BOM) of the tool.
- Employee identical hardware throughout the product line to improve economy of scale.
- Minimize non-productive hardware, sensors and interconnect complexity.
- Do not compromise on component quality, minimize the number of components.
- Minimize Tool Footprint
- Stack processes where it makes sense to do so
- Integrate wafer handling and processes to eliminate wasted space
- Maximize Reliability (note the very same responses to minimizing BOM costs improve reliability a clear Win-Win.
- Employee identical hardware throughout the product line to improve economy of scale. (Enables testing and long term improvement)
- Minimize non-productive hardware, sensors and interconnect complexity. (components that are not there cannot fail)
- Do not compromise on component quality, minimize the number of components. (The highest quality components fail less frequently)
- Minimize consumption of materials cost. (Things like photo resist, solvents, gases, etc.)
- Improve tool functionality while lowering BOM cost
- Creatively work with customers to take advantage of improved tool functionality.
- Use software to improve functionality as well as hardware. Software has zero replication cost.
- Increase Tool Throughput
- Provide wafer handling capability at low cost that balances process times with minimum handling overhead time. Provide smart robotics capability.
Use “Small Grain” tools. By this we mean tools that can be provided in small increments of production while at the same time minimizing COO and Investment in absolute terms. All of the above items support this Aspect.