Category Archives: BEOL

The Photolithography Process and Its Use In Wafer Level Chip Scale Packing (WLCSP)

The basic concept of Wafer Level Chip Scale Packaging (WLCSP) is to employ more or less the same techniques used in making a semiconductor device to create its packaged form. For convenience we will define the device manufacture as having been done in the Front End of the Line (FEOL) and the WLCSP packaging as being done in the Back End of the Line (BEOL). As in the manufacture of the device, the manufacture of the package is done en masse so that economy of scale minimizes cost and it is done in the same format namely on the wafer. There are however differences that arise that creates new needs in the photolithographic processing equipment that performs the Photolithography task. In this Blog we examine some of the most critical of those differences. We begin with the wafer itself.

The Wafer. The value of the wafer at this stage of the process is very high as it has been fully processed and the chips that make up the wafer are at their full value as functional devices. Also because all of the films needed to make a functional device up to that point have been applied the wafer is no longer a nearly perfectly flat object but is rather warped.

The character of the Photoresist to be applied. As the geometries to be created are rather large by comparison to those created in the FEOL the resist tends be far thicker and when bonding bumps are created the photoresist can be used to form a sort of mold into which the desired bump material is plated. In the BEOL resist thickness will typically be on the order of several microns up to 100 microns. The economics of packaging (BEOL) differ from those in the device (FEOL) manufacturing. Because geometries are generally larger lower cost resists can be used and often are. Photoresist processing equipment needs to accommodate these differences and must have a Low Cost of Ownership (Low COO) on a per wafer basis than FEOL tools.

Then the equipment should be able to handle warped wafers, with virtually NO wafer damage, it must be able to use thicker resists and perform the soft bake in an enclosure that does not need to be cleaned frequently if at all and it must be miserly in consumption of photoresist. The equipment itself should have high throughput, low footprint and low cost and material consumption.

Check out our other blogs discussing the BEOL from different points of view.

Lowering Cost of Ownership (COO) “Track” Tools in Back end of the Line (BEOL) Thick Resist Film processes

As it becomes apparent that the adoption of new process nodes has been significantly slowed down due to availability and cost of next generation FEOL lithography technologies, it becomes ever more important that the continuation of cost reductions and functionality improvements that have driven the growth of the Semiconductor industry over the last 40 years be sought elsewhere. Some of the investment heretofore focused on the FEOL “bleeding edge” technology should now be refocused more in BEOL Photo resist lithography for packing where the lower hanging fruit lies. This will require simplification of processes and reduction in material costs wherever possible while at the same time improving process control, yields and functionality and reducing photo resist processing tool costs.

One way to reduce costs is by substantially reducing waste in photolithographic processing technology. It has long been noted by just about anyone who performs spin processing on Photoresist Track equipment that there is an enormous amount of waste in the process as most of the Photoresist material consumed in the process is actually thrown off the wafer during the spin process and wasted. Textbooks in disusing the process point out the wastefulness of the process. The waste becomes especially meaningful in BEOL WLCSP, 2.5D and 3D processing where thicker resist films need to be cast. Multiple spins to achieve the film thickness required exacerbates the waste, while increasing Photoresist viscosity so that the thicker films can be cast adds substantially to equipment costs as the pumps required to pump the material can cost well into the 5 figures in US Dollars. Multiple spins also require more Photoresist track equipment for multiple trips through the equipment. The high viscosities also make elimination of bubbles a constant struggle further increasing costs. The film is formed during the spin process and then baked typically on a hot plate to remove additional solvent to render the film stable and photo definable. All of the foregoing tends to substantially increase photo resist processing costs in the Back End of the Line (BEOL) lithography for Wafer level Chip Scale Packaging (WLCSP). Another avenue is to use expensive chemically amplified resist (CAR) systems, which have the effect of improving CD control and aspect ratio’s in a single coat, however further increasing material cost substantially.

The engineers at S-Cubed™ have invented a new process…FastSpin™ that addresses all of these cost/complexity issues. In the new process (patents applied for) the film is not cast so much as wet formed by spinning the wafer under exquisite servo control for a very short time, subsequently processed to render the film stable and photo definable. The wet film is maintained in the wet state and is allowed to level, allowing for planar coatings over topography. The process not only substantially reduces photo resist consumption for both standard and CAR resists, it also substantially reduces the cost of the photo resist processing tools, Photo resist track, by reducing the number of spin processors required for a given spin processor tool throughput.

Please request further information regarding S-Cubed™ FastSpin™ click on the link:

https://www.s-cubed.com/contact-us/

Creating Value With “Track” Tools in Back end of the Line (BEOL)

The Semiconductor Industry has for years followed the path of “Moore’s” Law. Gordon Moore’s forecast that the industry would every 18 months double the number of transistors in a given area, thereby increasing value while reducing cost. His prediction has held true for about 20 years, and is now faltering. However the effect of his prediction can and will continue into the foreseeable future but rather than the aerial rule obtaining on silicon it will now move increasingly to the package. That trend is now beginning in earnest and the improvements in functionality and cost will occur more and more in the Back End of the Line (BEOL) /packaging of function. The driving economic factor is clearly the proliferation of mobile devices of all sorts.

While the technology of the photolithographic processing remains very similar there are important details that must be addressed if the tool sets of track and lithography are to be optimized for the new needs. BEOL processes involve different economic drivers, which must be accommodated by the Cost of Ownership (COO) models for BEOL tool sets versus Front End of Line (FEOL) tool sets. For more detail on the subject please see our BLOG entitled “Why Back End of Line (BEOL) Photoresist “Track” tool are and must be different from Front End of Line (FEOL) Photoresist processors.”

Why Back End of Line (BEOL) Photoresist “Track” Tools are and must be Different from Front End of Line (FEOL) Photoresist Processors

In earlier writings we have discussed cost of ownership issues (COO) related to photoresist processing tools. In this entry, we will discuss the important functional differences between tools generally intended for the FEOL, and those more adaptable to the needs of BEOL wafer fabrication.

As the semiconductor industry has packed more and more functionality and speed into ever smaller chips (here one almost always must refer to Moore’s Law well know to those in the industry), the size and cost of the packaging of the chip has made necessary the creation of new types of wafer processing, which is needed to do wafer-level chip scale packaging. In this specific technology, photolithographic processing is used so chip outputs and inputs can be repositioned, so as to adapt to interconnect circuitry directly without the intervention of a typical pin out type package. In this case the chip is “rewired” and “bumped” so that it can be “flipped and bonded” directly to the chip interconnect circuitry. Such rewiring and wafer bumping is accomplished on the finished device wafer prior to singulation of the wafer into chips.

While the patterning concept is identical to that required to make the chip itself in practice, the geometries are far larger and the need for organic insulating film more prevalent than in the creation of the chip. This means that the spin cast films are much thicker and there is far more effluent of material leaving the wafer during the required “bakes” done in the thermal modules of the requisite tools. These thicker films require the following considerations in the design and implementation of the tool.

  • The cost of the process must be kept low, thus requiring tools with a low COO.
  • The spin cup must be designed to handle thicker films and capable of modulating spin exhaust conditions on a step-by-step basis throughout the process recipe.
  • The higher viscosity resists that are used to spin the thicker films means pumps must be geared to accomodate those viscosities.
  • The higher viscosity resist requires that the dispense height be preferably programmable rather than adjustable so that it can be varied during the dispense.
  • The much thicker films evolve far more solvent and other effluent requiring that the effluent be directed away from cold surfaces where it can condense and require frequent bake module cleaning, or create defective films owing to effluent reflux.

While FEOL tools may be utilized in BEOL, their high cost can be prohibitive, and their performance while tuned to the FEOL is not appropriate to the BEOL provider.

System Granularity and Management of Change and Growth

A very important aspect of cost of ownership (COO) of tools that include spin coaters and developers (often referred to a photoresist track tools) in the back end of line (BEOL), MEMS, and patterned sapphire substrate (PSS) processing-type processing lines is one that does not appear on the COO software packages. Often referred to as “opportunity cost,” it is specifically defined as “the difference in return between an investment one makes and another that one chose not to make.” A high degree of system “granularity” enables appropriate investment as customer needs evolve. Ultimately this can substantially reduce opportunity cost. Granularity specifically relates to tools sized to the capacity need, as well as properly balanced for output in order to minimize waste. Lets look at how that works, in the context of opportunity cost.

Since opportunity cost is always a comparison of the path chosen to the path that was not chosen, we will compare two hypothetical systems whose COO on a per wafer output basis is identical, but its granularity is different. Granularity will tend to go up in integer values. Let us suppose a system whose out put is equal to one unit of capacity, (i.e., 2000 wafers per month) and another whose out put is equal to two units of capacity (i.e., 4000 wafers per month). If the need is for one unit of capacity, then if the COO is the same and the more granular system is the clear choice. If it is two units of capacity then the choices are equal. However what happens when it is three units of capacity; then four; then five? Capacity needs often develop in incremental steps over the long term instead of in immediate doublings. The investment in the “granular approach” is obviously the more appropriate forward-thinking plan. As needs eventuate, so that capacity can be adjusted to market needs at the lowest possible cost in capital spread over time.