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The Photolithography Process and Its Use In Wafer Level Chip Scale Packing (WLCSP)

The basic concept of Wafer Level Chip Scale Packaging (WLCSP) is to employ more or less the same techniques used in making a semiconductor device to create its packaged form. For convenience we will define the device manufacture as having been done in the Front End of the Line (FEOL) and the WLCSP packaging as […]

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Lowering Cost of Ownership (COO) “Track” Tools in Back end of the Line (BEOL) Thick Resist Film processes

As it becomes apparent that the adoption of new process nodes has been significantly slowed down due to availability and cost of next generation FEOL lithography technologies, it becomes ever more important that the continuation of cost reductions and functionality improvements that have driven the growth of the Semiconductor industry over the last 40 years […]

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Creating Value With “Track” Tools in Back end of the Line (BEOL)

The Semiconductor Industry has for years followed the path of “Moore’s” Law.  Gordon Moore’s forecast that the industry would every 18 months double the number of transistors in a given area, thereby increasing value while reducing cost.  His prediction has held true for about 20 years, and is now faltering.  However the effect of his […]

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EUV Quo Vadis

“No tree grows to the sky”, my friend Karol Ubanek, the founder of Tencor, uttered these words of wisdom.  They come to mind whenever I read an article or report on the subject of EUV.  The amount of money and effort that are being poured into the development of the technology is nothing short of […]

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System Granularity and Management of Change and Growth

A very important aspect of cost of ownership (COO) of tools that include spin coaters and developers (often referred to a photoresist track tools) in the back end of line (BEOL), MEMS, and patterned sapphire substrate (PSS) processing-type processing lines is one that does not appear on the COO software packages.  Often referred to as […]

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On Data…Innovation…and Nature

In our first post, we made the following point about companies that are not the huge Foundries; “such companies will use their own creativity and drive to gain a market advantage owing to their expertise in both designing and building their chips. Such companies will need to find ways to lower their manufacturing costs by […]

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Why Back End of Line (BEOL) Photoresist “Track” Tools are and must be Different from Front End of Line (FEOL) Photoresist Processors

In earlier writings we have discussed cost of ownership issues (COO) related to photoresist processing tools. In this entry, we will discuss the important functional differences between tools generally intended for the FEOL, and those more adaptable to the needs of BEOL wafer fabrication. As the semiconductor industry has packed more and more functionality and […]

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The Argument for New Vs Refurbished Used Photoresist Process Equipment

In an earlier BLOG we discussed “Lowering the Cost of Ownership (COO) of Spin Process Tools.” we did not discuss the fact that the customer does have an option to purchase a used, “used and refurbished” or “as is” version of a tool built at some point in the past as another means of lowering […]

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Lowering the Cost of Ownership (COO) of Spin Process Tools

In our last BLOG we discussed the need to lower the COO of the tools of production for those who are both designing and building their chips. The issue that we attempt to address here is how does one make that happen and at the same time improve functionality permitting the customer to do things […]

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The Outlook for the Semiconductor Industry

Does the word “commodity” come to mind; how about the word “innovation?” OK, now try “risk.” The question of the outlook for semiconductor production worldwide is a mixture of the feelings and fears, thoughts and challenges associated with the relationship between those three words, Commodity, Innovation and Risk… Now look at the Global Semiconductor Industry […]

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